The present invention relates to an edge-triggered D-Flip-Flop circuit, having a master circuit and a slave circuit.
The D-Flip-Flop, also known as data-Flip-Flop, is a fundamental circuit block in digital logic circuits. An edge-triggered D-Flip-Flop with master-slave-configuration is presented, for example, in Tietze, Schenk: Halbleiter-Schaltungstechnik, 10th edition, pages 237-40.
Data-Flip-Flops have a wide field of application, including memories, especially DRAMS, microprocessors, VLSI circuits, and so on. In these fields, low power consumption, high speed and smallest possible chip area are the main targets of the present chip manufacturing industry.
Present implementations of master-slave D-Flip-Flops normally include CMOS transmission gates, inverters and other logic gates.
A master-slave D-Flip-Flop having a master block followed by a slave block, both of which comprise switches and latches, is presented in U.S. Pat. No. 5,784,384 (see German published patent application DE 196 36 083 A1). The arrangement described therein comprises switches implemented as transmission-gates in order to achieve determined voltage levels representing logic 0 and 1, respectively.
These master-slave D-Flip-Flop implementations require a relatively large chip area, which is especially disadvantageous when used in mass applications such as memory chips or microprocessor chips.
It is accordingly an object of the invention to provide an edge-triggered data flip-flop using a master-slave-configuration, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which can be integrated requiring less chip area and is suitable for mass applications such as memories or microprocessors.
With the foregoing and other objects in view there is provided, in accordance with the invention, an edge-triggered D-Flip-Flop circuit, comprising:
a master circuit having a data input, a master switch in the form of an n-channel metal oxide semiconductor field-effect transistor controlled by a clock signal and connected with one end to the data input terminal, and a first inverter having an input terminal connected to the master switch and an output terminal; and
a slave circuit having a slave switch in the form of an n-channel metal oxide semiconductor field-effect transistor controlled by the clock signal and connected to the output terminal of the first inverter, a second inverter having an input terminal connected to the slave switch and an output terminal, and a feedback-loop comprising a feedback-switch and a third inverter connected between the input terminal and the output terminal of the second inverter.
In other words, the objects of the invention are achieved by an edge-triggered D-Flip-Flop circuit having a master circuit and a slave circuit. The master circuit comprises a master switch controlled by a clock signal and connected with one end to a data input terminal and comprising a first inverter having an input terminal and an output terminal, the input terminal being connected to the master switch; and the slave circuit comprises a slave switch controlled by the clock signal and connected to the output terminal of the first inverter, a second inverter having an input terminal and an output terminal, the input terminal being connected to the slave switch, and a feedback-loop comprising a feedback-switch and a third inverter and being connected to the second inverter input and output terminals. Importantly, the master switch and the slave switch are n-channel MOSFETs (metal oxide semiconductor field-effect transistors).
Advantageously, the feedback-loop is a regenerative feedback-loop.
The Flip-Flop circuit described saves a considerable amount of chip area and shows improved performance especially when used extensively in memory or microprocessor circuits.
By using N-MOSFETS instead of transmission gates, the circuit arrangement given is faster and appropriate for higher frequencies.
The inverters, especially the first inverter, may serve as a level-shifter to provide determined voltage levels for logic 0 and 1, respectively.
In addition, the circuit is easily adaptable to lower supply voltages such as 1.2 or 1.4 volts by replacing the N-MOS switches with low threshold voltage N-MOSFETS.
In accordance with an added feature of the invention, means are provided to set and reset an information stored in the slave circuit. In some applications, it is preferable to have the possibility to set and reset the information stored in the slave circuit and therefore provide direct possibility to influence the state of the output terminal of the slave circuit or the D-Flip-Flop circuit respectively.
In accordance with an additional feature of the invention, a set switch is provided with one end connected to the input terminal of the second inverter and another end connected to ground potential.
In accordance with another feature of the invention, a reset switch is provided having one end connected to the output terminal of the second inverter, and another end connected to ground potential. These set and reset means provided allow an implementation of a master-slave D-Flip-Flop having set and reset input terminals with very small chip area.
In accordance with a further feature of the invention, the master and slave switches are pass-transistors. Pass-transistors require very low chip area, and therefore the positive edge-triggered D-Flip-Flop circuit can be integrated with very low chip area.
In accordance with a concomitant feature of the invention, the pass-transistors are MOSFETs. Preferably, MOSFETs of an enhancement type can be used. Advantageously, the set, reset and feedback-switches are also implemented using enhancement type MOSFETs.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a Edge-Triggered D-Flip-flop Circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.